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NoMaY-jp’s ポイント

NoMaY-jp 201 ポイント.

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NoMaY-jp's ポイント

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7月 11, 2023 Commented Hello support team, I have implemented the new workaround into my examples of RX SmartConfigurator as below. My next step is to post an issue to the repository of Renesas RX driver package. https://github.com/NoMaY-jp/RX_SmartConfigurator_examples_RXTB_GNURX/blob/751f319/30_UART_Printf/tb_rx671/src/linker_weakdef_rvectors.S https://github.com/NoMaY-jp/RX_SmartConfigurator_examples_RXTB_GNURX/blob/751f319/30_UART_Printf/tb_rx671/src/linker_script.ld#L19-L35 https://github.com/NoMaY-jp/RX_SmartConfigurator_examples_RXTB_GNURX/blob/751f319/30_UART_Printf/tb_rx671/CMakeLists.txt#L50 ---- https://github.com/renesas/rx-driver-package/issues Best regards, NoMaY

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6月 26, 2023 Asked GCC for Renesas RX 8.3.0.202202 or later needs `Path` setting

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6月 17, 2023 Commented Hello support team, Thank you for the un-deprecation and better solution. https://llvm-gcc-renesas.com/release-notes/rx/latest/8.3.0.202305/release_notes.pdf#page=2 https://llvm-gcc-renesas.com/wiki/index.php?title=RX_automatic_interrupt_vector_entry_usage Do you talk with Renesas about the solution? (I made a post about your solution on the Renesas Rulz Japanese Forum: https://community-ja.renesas.com/cafe_rene/forums-groups/mcu-mpu/rx/f/forum5/5079/cc-rx-gnurx-c99-_pragma-fit/49382#49382) Best regards, NoMaY

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2月 24, 2023 Commented Hello support team, Are there any new topics? The following thread was closed with the status of `Verified Answer`. Is there any migration plan of FIT and RX SmartConfigurator due to future deprecation of GNURX's Automatic interrupt vector entry generation feature? https://community.renesas.com/mcu-mpu/rx/f/rx-forum/29337/is-there-any-migration-plan-of-fit-and-rx-smartconfigurator-due-to-future-deprecation-of-gnurx-s-automatic-interrupt-vector-entry-generation-feature Best regards, NoMaY

+2

1月 29, 2023 Asked LLVM for Renesas RL78 10.0.0.202212 can’t assemble the src/smc_gen/r_bsp/mcu/all/start.S while 10.0.0.202209 can do it

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12月 9, 2022 Commented Hello support team, Thank you for improving this in the GCC 8.3.0.202204-GNURX. I get the following code even in the CASE B. CASE B: with -mdfp rx-elf-gcc -std=gnu99 -O3 -misa=v3 -mdfpu -mtfu=intrinsic,mathlib -Wa,-adln=rxv3_tfu_sinf_cosf.lst -c rxv3_tfu_sinf_cosf.c 1 .file "rxv3_tfu_sinf_cosf.c" 2 .section P,"ax" 3 .global _rot 5 _rot: 6 0000 7E A7 push.l r7 7 0002 FB EE 14 14 08 mov.L #0x81414, r14 8 0007 E3 E1 mov.L r1, [r14] 9 0009 FB 4E 10 14 08 mov.L #0x81410, r4 10 000e EC EF mov.L [r14], r15 11 0010 A8 2F mov.L 4[r2], r7 12 0012 A0 49 mov.L r1, 4[r4] 13 0014 EC 45 mov.L [r4], r5 14 0016 FC 8F 7F fmul r7, r15 15 0019 EC 27 mov.L [r2], r7 16 001b FC 8F 75 fmul r7, r5 17 001e FC 83 F5 fsub r15, r5 18 0021 E3 35 mov.L r5, [r3] 19 0023 E3 E1 mov.L r1, [r14] 20 0025 EC EE mov.L [r14], r14 21 0027 EC 2F mov.L [r2], r15 22 0029 A0 49 mov.L r1, 4[r4] 23 002b EC 45 mov.L [r4], r5 24 002d A8 2C mov.L 4[r2], r4 25 002f FC 8F FE fmul r15, r14 26 0032 FC 8F 45 fmul r4, r5 27 0035 FC 8B E5 fadd r14, r5 28 0038 A0 3D mov.L r5, 4[r3] 29 003a 3F 77 01 rtsd #4, r7-r7 31 .ident "GCC: (GCC_Build_20221126) 8.3.0.202204-GNURX 20190222" In the Release Notes of the GCC 8.3.0.202204-GNURX: 2. [Improvement] Negated floats getting promoted to double In previous releases, negation of floats resulted in their promotion to double, generating sub-optimal code if doubles were represented on 8 bytes. In the current release of the compiler, promotion will no longer happen when negating floats. Best regards, NoMaY P.S. I notice that the two generated codes are slightly different. (It isn't a problem.) CASE A: without -mdfpu rx-elf-gcc -std=gnu99 -O3 -misa=v3 -mtfu=intrinsic,mathlib -Wa,-adln=rxv3_tfu_sinf_cosf.lst -c rxv3_tfu_sinf_cosf.c 1 .file "rxv3_tfu_sinf_cosf.c" 2 .section P,"ax" 3 .global _rot 5 _rot: 6 0000 7E A7 push.l r7 7 0002 FB FE 14 14 08 mov.L #0x81414, r15 8 0007 E3 F1 mov.L r1, [r15] 9 0009 FB EE 10 14 08 mov.L #0x81410, r14 10 000e EC F4 mov.L [r15], r4 11 0010 A8 2F mov.L 4[r2], r7 12 0012 E7 E1 01 mov.L r1, 4[r14] 13 0015 EC E5 mov.L [r14], r5 14 0017 70 44 00 00 00 80 add #-2147483648, r4 <-- HERE 15 001d FC 8F 74 fmul r7, r4 16 0020 EC 27 mov.L [r2], r7 17 0022 FC 8F 75 fmul r7, r5 18 0025 FC 8B 45 fadd r4, r5 <-- HERE 19 0028 E3 35 mov.L r5, [r3] 20 002a E3 F1 mov.L r1, [r15] 21 002c EC F4 mov.L [r15], r4 22 002e EC 2F mov.L [r2], r15 23 0030 E7 E1 01 mov.L r1, 4[r14] 24 0033 EC E5 mov.L [r14], r5 25 0035 A8 2A mov.L 4[r2], r2 26 0037 FC 8F F4 fmul r15, r4 27 003a FC 8F 25 fmul r2, r5 28 003d FC 8B 45 fadd r4, r5 29 0040 A0 3D mov.L r5, 4[r3] 30 0042 3F 77 01 rtsd #4, r7-r7 32 .ident "GCC: (GCC_Build_20221126) 8.3.0.202204-GNURX 20190222" CASE B: with -mdfp rx-elf-gcc -std=gnu99 -O3 -misa=v3 -mdfpu -mtfu=intrinsic,mathlib -Wa,-adln=rxv3_tfu_sinf_cosf.lst -c rxv3_tfu_sinf_cosf.c 1 .file "rxv3_tfu_sinf_cosf.c" 2 .section P,"ax" 3 .global _rot 5 _rot: 6 0000 7E A7 push.l r7 7 0002 FB EE 14 14 08 mov.L #0x81414, r14 8 0007 E3 E1 mov.L r1, [r14] 9 0009 FB 4E 10 14 08 mov.L #0x81410, r4 10 000e EC EF mov.L [r14], r15 11 0010 A8 2F mov.L 4[r2], r7 12 0012 A0 49 mov.L r1, 4[r4] 13 0014 EC 45 mov.L [r4], r5 14 0016 FC 8F 7F fmul r7, r15 15 0019 EC 27 mov.L [r2], r7 16 001b FC 8F 75 fmul r7, r5 17 001e FC 83 F5 fsub r15, r5 <-- HERE 18 0021 E3 35 mov.L r5, [r3] 19 0023 E3 E1 mov.L r1, [r14] 20 0025 EC EE mov.L [r14], r14 21 0027 EC 2F mov.L [r2], r15 22 0029 A0 49 mov.L r1, 4[r4] 23 002b EC 45 mov.L [r4], r5 24 002d A8 2C mov.L 4[r2], r4 25 002f FC 8F FE fmul r15, r14 26 0032 FC 8F 45 fmul r4, r5 27 0035 FC 8B E5 fadd r14, r5 28 0038 A0 3D mov.L r5, 4[r3] 29 003a 3F 77 01 rtsd #4, r7-r7 31 .ident "GCC: (GCC_Build_20221126) 8.3.0.202204-GNURX 20190222" Best regards, NoMaY

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12月 9, 2022 Commented Hello support team, Thank you for improving this in the GCC 8.3.0.202204-GNURX. And I hope future improvement for the case that such push/pop sequence is not necessary. (I understand/remember that `optimizations are always in the scope of future releases`.) In the Release Notes of the GCC 8.3.0.202204-GNURX: 1. [Improvement] DCMR register not getting saved/restored on function entry/exit In the current release, the DCMR register will be saved on function entry and restored on function exit. Best regards, NoMaY

+1

12月 7, 2022 Commented Hello support team, I have posted my idea to the Renesas Rulz English Forum. reply - Is there any migration plan of FIT and RX SmartConfigurator due to future deprecation of GNURX's Automatic interrupt vector entry generation feature? https://community.renesas.com/mcu-mpu/rx/f/rx-forum/29337/is-there-any-migration-plan-of-fit-and-rx-smartconfigurator-due-to-future-deprecation-of-gnurx-s-automatic-interrupt-vector-entry-generation-feature/100827#100827 Best regards, NoMaY

+1

12月 6, 2022 Commented Hello support team, Thank you for reconsidering the deprecation. I agree that we need a solution more than a workaround. I'm getting an idea (perhaps) more than a workaround. I'm posting the idea to Renesas Rulz Japanese Forum one by one but I'm sorry that it is Japanese language as of today. Please don't worry about my consideration because I understand that it is just one of ideas for solving the problem which is caused by the combination of the feature and the -gc-section option. Best regards, NoMaY

+1

12月 3, 2022 Commented Hello support team, I have posted the following issue to the Renesas Rulz. Is there any migration plan of FIT and RX SmartConfigurator due to future deprecation of GNURX's Automatic interrupt vector entry generation feature? https://community.renesas.com/mcu-mpu/rx/f/rx-forum/29337/is-there-any-migration-plan-of-fit-and-rx-smartconfigurator-due-to-future-deprecation-of-gnurx-s-automatic-interrupt-vector-entry-generation-feature Best regards, NoMaY

+2

12月 1, 2022 Asked Please don’t remove Automatic interrupt vector entry generation feature because RX SmartConfigurator strongly depends on it and there is an easy workaround

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12月 1, 2022 Commented Hello support team, Thank you for the reply. I get the following code for both case (with and without -mdfpu) using -fno-math-errno. 1 .file "rxv3_fpu_sqrtf.c" 2 .section P,"ax" 3 .global _RXv3_FPU_sqrtf 5 _RXv3_FPU_sqrtf: 6 0000 FC A3 11 fsqrt r1, r1 7 0003 02 rts 9 .ident "GCC: (GCC_Build_20220528) 8.3.0.202202-GNURX 20190222" Best regards, NoMaY P.S. I found the following pages that may help myself in the future. https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#index-fno-math-errno https://stackoverflow.com/questions/57676693/which-functions-are-affected-by-fno-math-errno https://stackoverflow.com/questions/57673825/how-to-force-gcc-to-assume-that-a-floating-point-expression-is-non-negative Best regards, NoMaY

+2

10月 26, 2022 Asked Difference of generated code regarding GNURX for RXv3 `float` operation between with and without -mdfpu (code – 2022/10/26)

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10月 25, 2022 Asked Difference of generated code regarding GNURX for RXv3 sqrtf(x) using -mrxv2-fsqrt between with and without -mdfpu (code – 2022/10/25)

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10月 24, 2022 Asked Wrong generated code regarding GNURX for RXv3 TFU mathlib hypotf(x, y) (code – 2022/10/24)

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10月 4, 2022 Asked Wrong generated code regarding GNURX for RXv3 DPFPU DCMR register missing push/pop sequence (code – 2022/10/04)

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9月 22, 2022 Commented Hello support team, Thank you for the reply. It is good to hear that the issue is planned to be fixed. Best regards, NoMaY

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9月 16, 2022 Asked Wrong generated code regarding GNURL78 far pointer access (code – 2022/09/14, 2022/09/15)

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6月 28, 2021 Commented Dear support team, Thank you for your reply. I have modified my code as the following screen copies and it works. Screen copies are here: https://japan.renesasrulz.com/cafe_rene/f/forum21/6968/nomay-jp-open-source-tools-for-renesas-website-questions-and-answers/38580#38580 Best regards, NoMaY

+2

6月 18, 2021 Asked GNURX 8.3.0.202102 doesn’t recognize DECNT register of RXv3

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